[blackguardx]

As an FPGA developer, I think this is a noble effort, but will be of limited use in porting their design (one of their stated goals).

Essentially all of the modules they are asking for "clones" of directly instantiate hardware primitives on the FPGA die. Many of the blocks are basically analog pieces that won't be easily synthesizable from Verilog. While the simulation would work with other tools, the block won't be able to be mapped in other FPGA architectures.

[Andrey_Filippov]

Not really many are "analog" and we already have GTX model. Some primitives are just buffers, some - memories (block RAM), one PLL. I do not think it is a "rocket science" to create functional models without precise timing.

As for different architectures - sure these will not work, but we keep all the primitives in "wrapper" modules to simplify porting. With missing primitives it will be possible to run complete simulation, after that you can start replacing primitives to match different devices.

[CamperBob2]

Yeah, that's absurd. It's like asking for C intrinsics to be implemented as functions.

Those primitives are just a way to force the synthesis tool to infer specific hardware features.

[duskwuff]

In the case of some of these primitives, like I/OSERDES -- high-speed input/output de/serializers -- they can't even be inferred. The only way you'll get one is if you specifically ask for it.