[ethbro]

I never thought about it that way (I find supercomputer comparch design fascinating for the tradeoffs chosen more than anything else), but the RISC/CISC alternatives can be thought of as an optimization for main memory latency.

If memory access is fast compared to the CPU, RISC designs are more optimal (as you can increase the CPU frequency). If memory accesses take longer than CPU execution, then CISC designs start to make more sense (do more complex things in one go once the CPU is done waiting on things to finally arrive).