[dkarchmer]

A little of both :-)

I was one of the biggest champions of opening our SW and worked hard to create open APIs to give access the device database and timing engine, even where there was no real business justification. The limitation was always what we could make usable without shipping an Altera engineer with the SW. A fair amount is available but unfortunately undocumented. If you look close enough, a some of the features in Quartus are written in plain Tcl, which you can reverse engineer.

[cottonseed]

Hi dkarchmer, thanks for your comments. I'm the author of arachne-pnr, the open-source pnr tool for the Lattice iCE40. One of my hopes is that by creating compelling open-source tools, it might be possible to change the value proposition for FPGA vendors to get involved in opening up the chip internals, although perhaps that's wildly optimistic. One of the hard parts is to get a realistic foothold. I like to think we're making some progress with the Icestorm project. I got a bug report from a user recently, and I quote, "We would like to do what we can to help fix your tools because the workflow is far superior." I know there's a world of difference between a big flagship FPGA and the iCE40.

I still like the analog with CPUs. If there was no gcc or LLVM and the vendors all had their own compilers, there would be little incentive to open up the ISA. In a word with gcc and LLVM, you're dead in the water if there isn't a port.

I was a little surprised to hear a big part of the job is documentation. How do the chip design teams communicate with the tool development teams? Or is there a problem with releasing internal documentation?