[oflordal]

Its been 10 years since standardization and the eda vendors are still whining about SystemVerilog implementation...

Interfaces was a great addition it serves more uses that simple structs (which were not available before SystemVerilog either). The primary use he doesn't seem to get is that it is a great place to put your interface assertions so all the intent of the interface end up in one place. The way this is typically done when SystemVerilog is only used for testbench/assertions is to put them in a separate file anyway so they don't have to be included in both the sender and receiver.

[krupan]

So use a class or a module instead of a struct. We probably could have solved multiple problems by simply allowing modules to be dynamic (like classes are), referance-able (like interfaces and classes are), and to support inheritance (like classes do) and saved ourselves at least three reserved words and the associated complexity and ambiguity of purpose and use.