Early ARM designs have group load/store commands. This goes against RISC philosophy. You cannot call ARM a RISC because of that. It is a CISC with simplified decoder.
I designed chips for living, despite being software engineer. Including, and not limited to, CPUs. In the design process I had to account for optimizing compilers and possible high-performance and low-energy versions.
So I am very sensitive to the misuse of "RISC trade mark".
Ideal RISC design is very easy to develop. It can be easily tailored to various application domains, including high-performance (OoO) and low-energy. RISC instruction semantics should be simple, all implementation details are hidden. In my opinion, there are only three RISC designs - DEC Alpha, IBM Power and RISC-V. Others contain various design issues that show their inner cogs and that had to be accounted in the designs different from the original one.
(in my MIPS implementation experience I've implemented 33% of MIPS commands in the first month and spent another month accounting for branch delay slot)
ARM contains three deviations from ideal RISC: user-visible PC (read of PC returns PC of command+8!), multi-cycle group load/store commands and condition codes. All three "features" make it difficult to design something different in performance than original ARM.