[pja]

So the ARM1 had no cache & no microcode. 15 user visible 32 bit registers, with some (Nos 10-15 IIRC) duplicated for use during interrupts (FIQ mode). I think a couple more registers were also duplicated for use during other interrupts. So bottom left looks like it might be the register bank. The square block at top right might be the instruction decode PLA?

There’s a block diagram for the ARM2 in this document: http://www.riscos.com/support/developers/asm/cpu.html I believe the ARM was much the same, with the exception of fewer banked registers & no integer multiplier, so the dedicated could probably trace the paths and make some guesses about where each block is located.

[pm215]

Yes, I think bottom left is the register bank -- you can see it is 25 elements horizontally by 32 vertically, and there are 25 total registers listed on the right (r0..r15 plus the svc/irq/fiq mode-banked copies of some of r10 through r14). Also I'm pretty sure the program counter (r15) is the far-left-hand-side, because that first row does not have cells in the bottom two bit positions or the top six (ARM1 used 26-bit addresses, hence the missing top six, and PC values are always 4-aligned, so no bottom two bits).