This is actually something I am currently working on. An extensible HDL which allows to gradually add abstraction layers (and operate solely on any chosen level), while keeping an ability to express anything down to gates.
I have not published the language yet, have to produce some nice looking examples first. But you can take a look at my approach to extensibility in general (the HDL language is using exactly the same thing) and some of the earlier mixing Verilog with C experiments here: https://github.com/combinatorylogic