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by nickpsecurity
3930 days ago
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"PowerPC, RISC-V, MIPS, SPARC, and other kinds of RISCy CPUs, however, don't fare nearly as well. These CPUs provide primitives that are far too atomic, and thus, to emulate a stack CPU, you literally need to translate each Machine Forth primitive into a sequence of RISC instructions." More evidence that maybe we should stop using Forth for this stuff. It's a weird language we don't otherwise use that enforces a specific model that majority of architectures don't even support. A simple, imperative language with macro's and inline assembly should do just fine. Maybe time to dust-off Modula-2 or something similar. It worked on constrained, diverse hardware. Astrobe put Oberon on ARM microcontrollers and is porting it to RISC-V so I'm sure it's doable. |
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Ada would like to have a word with you. :-)