I wonder if this would fit in a Lattice ICE40 FPGA so that Xilinx ISE could be avoided (very buggy) and open source tools like Yosys could be used instead.
It should fit, as you said, but the last time I tried it the VHDL front-end for Yosys was not up to it. That might have changed as it was a few years ago.
It is (I think) much better now - it is ghdl as a plugin synthesising to yosys IR. The nightlies from https://github.com/YosysHQ/fpga-toolchain have it all ready to go.
Looks interesting, it is known that J1 is very tiny, how many can fit in the Spartan-6 XC6LX16 mentioned, do you have plan of create a multi-core system with this?
I almost got VHDL STDIN/STDOUT <-> UART <-> H2 core working, which would have allowed you to interact at run time with the VHDL simulation, but I do not think it is possible to do without using non-standard extensions, which is a shame. The attempt is still in "tb.vhd" and can be turned on by modifying "tb.cfg". I was quite impressed that I managed to get a VHDL program that could process a text file at run time so I did not have to keep compiling it.
Yes, although you will only get waveforms as an output. There is a fully interactive GUI simulator (type "make gui-run" to build it and run it), and a command line simulator as well (just type "make run").