This is a very good and detailed intro into the basics of FPGA debugging, or specifically in this case using the FPGA to stimulate and monitor an external device.
Using the ILA core would allow you to monitor the outputs in real time and draw a waveform which may be more useful for advanced tests. Some additional ideas could be:
1) loading a BRAM with some vectors and then playing them automatically at higher speed and monitoring the result.
2) similar to the above but driving vectors from a soft processor such as microblaze for more automated debug/stimulus
I was going to suggest hardware in the loop simulation, which used to allow a simulator to stimulate and monitor hardware - but it appears this now supports only system-generator and HLS use cases, and the generic RTL use case is deprecated.
So running a 6502 on an Artix-7 or W65C02S, is this more or less the most you can get out of it. That is does it max out the available logical units on the respective chips? Also do you get a 1:1 speed, when it comes to frequency etc?
"Artix 7" is a family of devices. The "Arty A7" he's using comes in 2 choices...the A7-35T for $119, or the A7-100T for $249. The picture seems to show the A7-35T.
The MEGA65 runs on the A200T variant of the Artix-7, and claims to be 50x faster than a Commodore64. Also, you can find a few different 32-bit soft cores booting linux on Artix-7 FPGAs.
(Though, as mentioned, the article is not about emulating a 6502 on an FPGA)
I would guess that even on the most inexpensive FPGA (iCE40 for example) you could run a 6502 at at least 20 MHz, and fit some display logic on there as well.
Using the ILA core would allow you to monitor the outputs in real time and draw a waveform which may be more useful for advanced tests. Some additional ideas could be:
1) loading a BRAM with some vectors and then playing them automatically at higher speed and monitoring the result.
2) similar to the above but driving vectors from a soft processor such as microblaze for more automated debug/stimulus
I was going to suggest hardware in the loop simulation, which used to allow a simulator to stimulate and monitor hardware - but it appears this now supports only system-generator and HLS use cases, and the generic RTL use case is deprecated.